A semiconductor element is, for example, flip-chip-mounted on a wiring substrate. The wiring substrate includes an electrode (pad), a solder resist, which includes an opening that exposes the electrode, and a bump, which is located on the electrode and projects from the opening of the solder resist. The semiconductor element is connected to the bump. The bump is formed, for example, through electrolytic plating. For example, a seed layer is formed on a surface of the solder resist, and electrolytic plating is performed using the seed layer as a power feeding electrode to form an electrolytic plating layer. The electrolytic plating layer undergoes a reflow process to form the bump. Japanese Laid-Open Patent Publication No. 2012-129369 and Japanese National Phase Laid-Open Patent Publication No. 2012-506628 each describe an example of such a wiring substrate (terminal structure).
The bump formed as described above is in contact with a wall surface of the solder resist defining the opening. The solder resist has a greater thermal expansion coefficient than the bump. Thus, when the temperature changes, stress applied to the interface between the solder resist and the bump may form cracks in the bump.